Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for digital integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design can be again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to the place-and-route process, this process typically begins with a circuit design described at a register transfer level. Using a place-and-route tool, a designer can place portions of the circuit design relative to each other in a geographic design environment. While these circuit design portions can correspond to segments of code in a hardware description language, they typically are represented in the geographic design environment as blocks. Once the blocks have been placed relative to each other, wiring lines can be routed between the blocks. These wiring lines represent the interconnections, such as data signal interconnections and clock signal interconnections, which will be formed between the components of the electrical device.
The routing of these wiring lines typically takes place in two stages: a coarse or track routing stage, in which groups of wires are routed together between blocks, and detailed routing where the position and buffering of individual wires are adjusted. For clock signal interconnections, the first routing stage often includes generating a clock tree in the circuit design. While the clock tree can propagate a clock signal from a root clock source to each clock-driven circuit in the circuit design, the clock tree generated in the first routing stage is often unbalanced due to transmission delays associated with variable distances that the clock signal travels through the clock tree to the various clock-driven circuits.
The second routing stage for clock signal interconnections is typically an iterative process, with repeated performance of clock tree synthesis (CTS) to alter the timing of the clock signaling in the circuit design. Conventionally, the initial performance of clock tree synthesis alters the clock tree to eliminate or minimize skew between clock signals, i.e., having the clock tree synchronously provide clock signals to each clock-driven circuit in the circuit design. After the clock tree has eliminated or minimized skew in the circuit design, at least one subsequent clock tree synthesis can be performed to selectively modify the clock tree to synchronize the timing of the clock signals with the timing of data signals in the circuit design. Although this selective clock tree modification can introduce a small amount of skew, it is often called useful skew, because it adds the skew to the circuit design in order to accommodate various data path delays between the clock-driven circuits.